Recent designs of some memory devices have memory cells that are integrated in a three-dimensional manner. In such a memory device, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction are provided, and a memory cell is formed at each intersection of a word line and a bit line. Further, a predetermined voltage is applied to one word line and one bit line to cause the memory cell at the intersection of the one word line and the one bit line to be selected so that writing or reading of data can be performed on the selected memory cell. However, if the memory cells are more highly integrated intersection, interference between the memory cells may occur.